Design and realization of fully integrated multiband and multistandard bi-cmos sigma delta frequency synthesizer

Wireless communication has grown, exponentially, with wide range of applications offered for the customers. Among these, WLAN (2.4-2.5GHz, 3.6-3.7GHzand 4.915- 5.825GHz GHz), Bluetooth (2.4 GHz), and WiMAX (2.500-2.696 GHz, 3.4-3.8 GHz and 5.725-5.850 GHz) communication standard/technologies have found largest use local area, indoor – outdoor communication and entertainment system applications. One of the recent trends in this area of technology is to utilize compatible standards on a single chip solutions, while meeting the requirements of each, to provide customers systems with smaller size, lower power consumption and cheaper in cost. In this thesis, RF – Analog, and – Digital Integrated Circuit design methodologies and techniques are applied to realize a multiband / standart (WLAN and WiMAX) operation capable Voltage- Controlled-Oscillator (VCO) and Frequency Synthesizer. Two of the major building blocks of wireless communication systems are designed using 0.35 μm, AMS-Bipolar (HBT)-CMOS process technology. A new inductor switching concept is implemented for providing the multiband operation capability. Performance parameters such as operating frequencies, phase noise, power consumption, and tuning range are modeled and simulated using analytical approaches, ADS® and Cadence® design and simulation environments. Measurement and/or Figure-of-Merit (FOM) values of our circuits have revealed results that are comparable with already published data, using the similar technology, in the literature, indicating the strength of the design methodologies implemented in this study

A fully integrated multiband frequency synthesizer for WLAN and WiMAX applications

This paper presents a fractional N frequency synthesizer which covers WLAN and WiMAX frequencies on a single chip. The synthesizer is fully integrated in 0.35μm BiCMOS AMS technology except crystal oscillator. The synthesizer operates at four frequency bands (3.101-3.352GHz, 3.379-3.727GHz, 3.7-4.2GHz, 4.5-5.321GHz) to provide the specifications of 802.16 and 802.11 a/b/g/y. A single on-chip LC - Gm based VCO is implemented as the core of this synthesizer. Different frequency bands are selected via capacitance switching and fine tuning is done using varactor for each of these bands. A bandgap reference circuit is implemented inside of this charge pump block to generate temperature and power supply independent reference currents. Simulated settling time is around 10μsec. Total power consumption is measured to be 118.6mW without pad driving output buffers from a 3.3V supply. The phase noise of the oscillator is lower than -116.4dbc/Hz for all bands. The circuit occupies 2.784 mm2 on Si substrate, including DC, Digital and RF pads

Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads

A new lab-on-chip transmitter for the detection of proteins using RNA aptamers

A new RNA aptamer based affinity biosensor for CReactive Protein (CRP), a risk marker for cardiovascular disease was developed using interdigitated capacitor (IDC), integrated in Voltage Controlled Oscillator (VCO) and output signal is amplified using Single Stage Power Amplifier (PA) for transmitting signal to receiver at Industrial, Scientific and Medical (ISM) band. The Lab-on-Chip transmitter design includes IDC, VCO and PA. The design was implemented in IHP 0.25μm SiGe BiCMOS process; post-CMOS process was utilized to increase the sensitivity of biosensor. The CRP was incubated between or on interdigitated electrodes and the changes in capacitance of IDC occurred. In blank measurements, the oscillation frequency was 2.464GHz whereas after RNA aptamers were immobilized on open aluminum areas of IDC and followed by binding reaction processed with 500pg/ml CRP solution, the capacitance shifted to 2.428GHz. Phase noise is changed from -114.3dBc/Hz to -116.5dBc/Hz

A 6-bit vector-sum phase shifter with a decoder based control circuit for x-band phased-arrays

This letter presents a 6-bit vector-sum phase shifter with a novel control circuitry for X-band phased-arrays using a 0.25-m SiGe BiCMOS technology. A balanced active balun and highly accurate I/Q network are employed to generate the reference in-phase and quadrature vectors. The desired phase is synthesized by modulating and summing the generated reference vectors using current steering VGAs that are controlled by a decoder based control circuit. The phase shifter resulted in a measured RMS phase error <2.8 between 9.6-11.7 GHz and <5.6 between 8.2-12 GHz, achieving 6-bit phase resolution. The chip size is 1.870.88 mm2, excluding pads. To the best of authors’ knowledge, this is the first demonstration of a digitally controlled 6-bit vector-sum phase shifter for X-band

High first-trimester neutrophil-to-lymphocyte and platelet-to-lymphocyte ratios are indicators for early diagnosis of preeclampsia

Objectives: The aim of our study is to determine whether first-trimester neutrophil-to-lymphocyte ratio (NLR) and plate­let-to-lymphocyte ratio (PLR) would be useful as new predictors of subsequent preeclampsia. Material and methods: Medical records of women with preeclampsia and healthy controls from a tertiary referral center were retrospectively evaluated. The two groups were compared in terms of clinical characteristics and first-trimester levels of hemoglobin, leukocyte, neutrophil, lymphocyte, platelet, NLR and PLR. Receiver operating characteristic curve (ROC) analysis was performed to identify the optimal NLR and PLR levels predicting preeclampsia. Results: Neutrophil (p &lt; 0.001), platelet (p &lt; 0.001), NLR (p &lt; 0.001) and PLR (p &lt; 0.001) levels were significantly elevated, whereas hemoglobin concentration (p = 0.003) was significantly lower in the group with preeclampsia as compared to the control group. On multivariate regression analysis, NLR (OR 1.43; 95% CI 1.21–1.76; p = 0.005) and PLR (OR 1.38; 95% CI 1.15–1.63; p = 0.008) were the most powerful predictive variables. The area under the ROC was 0.716 and 0.705 for NLR and PLR, respectively. The cut-off values of NLR ≥ 3.08 and PLR ≥ 126.8 predicted preeclampsia with the sensitivity of 74.6% and 71.8% and specificity of 70.1% and 72.4%, respectively. Conclusions: High NLR and PLR during the first trimester are independent predictors of subsequent preeclampsia

Figure 1: Simple block diagram of a SiGe BiCMOS On chip T/R module 4-Bit SiGe Phase Shifter using Distributed Active Switches and Variable Gain Amplifier For X-Band Phased Array Applications

Abstract-This paper presents a 4-bit digitally controlled phase shifter for X-band (8-12.5 GHz) phased-arrays, implemented in 0.25-µm SiGe BiCMOS process. Distributed active switches are utilized in first three bits. On-chip inductances are used to provide 22.5° phase shift steps. The placement and the geometry of these inductances are optimized for minimum phase error and insertion loss. In order to compensate the gain variations of this stage, a single stage variable gain amplifier is used. The fourth bit which provides 0/180° phase shift is obtained in third amplification stage, with switching between common basecommon emitter configuration. With utilization of this technique overall phase error is significantly decreased and overall gain is increased. The phase shifter achieves 7dB gain with 3 dB of gain error. 360° phase shift is achieved in 4 bit resolution with a phase error of 0.5° at center frequency of 10GHz, and maximum 22° phase error in 4.5 GHz bandwidth. The chip size is 2150 µm x 1040 µm including the bondpads. These performance parameters are comparable with the state of the art using similar technology

An x-band 6-bit active phase shifter

This paper presents a 6-bit active phase shifter using a new vector-sum method for X-band (8-12 GHz) phased arrays in 0.13 mu m SiGe BiCMOS process. An RC filter is used to generate two orthogonal vectors which are then fed into four VGAs, two using the common-base and two using the common-emitter topology. This generates 4 vectors of 0 degrees, 90 degrees, 180 degrees and 270 degrees which are scaled and added by varying the gains of the VGAs to generate any phase between 0-360 degrees. The gains of the VGAs are adjusted with analog voltage control using the current-steering method. The outputs of the VGAs are connected together with a common load in order to add the vectors in current-domain. The phase shifter achieves < 5.6 degrees RMS phase error over 8-12 GHz and < 3.1 degrees RMS phase error over 9-11 GHz. The phase shifter has a power consumption of 16.6 mW from a 2V supply. The chip size is 850 mu m x 532 mu m including the probing pads. These performance parameters are comparable with the state of the art of the technology in literature

A wideband low noise SiGe medium power amplifier for x-band phased array applications

This paper presents a Medium Power Amplifier (MPA) for X-Band Phased Array RADAR applications in 0.25 mu m SiGe technology. The MPA is designed such that it achieves high output power and low noise simultaneously that enables its use in Transmitter/ Receiver (T/R) core module as a Low Noise Amplifier (LNA). The MPA achieves 23.6dB peak gain and 17.3dB maximum output power at 10GHz with a power consumption of 190mW. Its input and output is matched in a 7 GHz of bandwidth, while its mean Noise Figure (NF) is about 3dB throughout the defined bandwidth. According to authors' knowledge, this work presents state-of-the-art wideband MPA performances in literature, with 7GHz of operational bandwidth and 17.3dBm output power